Researchers propose nanowire transistor with integrated memory for future supercomputers


The ability to get the memories and processors of computer systems to work faster together has been a bottleneck in technological development for many years. In a new development, researchers at the Lund University, Sweden have proposed a new solution to integrate a memory cell with a processor, which allows faster computations as they happen in the memory circuit itself.

An article published in Nature Electronics demonstrates a new configuration for processors and memories wherein a memory cell is combined with a vertical transistor selector all at a nanoscale. This brings improvements in speed and energy efficiency, scalability in comparison with current mass storage solutions.

The fundamental challenge is that anything that requires large amounts of data to be processed such as ML and AI requires speed and more capacity. In order to attain this, proximity of the memory and processor is required. Furthermore, it must be possible to perform calculations in an energy-efficient manner.

The problem of computations of processors happening at much faster speed than the speed of the memory unit is well known for many years. In technical parlance, this is termed as ‘von Neumann bottleneck.” The roadblock is related to separate memory and computation units, and it takes time to disseminate information to and fro via data bus, which restricts speed.

Over the years, processors have developed considerably. On the memory aspect, storage capacity has increased steadily but things have been mostly unchanged on the function side.

For traditional processors, the limitation is related to the making of circuit boards with units positioned next to each other on a flat surface. At present, the change lies to build processors vertically in a 3D configuration and to integrate the memory and processor.

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